Detailed information about the course

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Winter School on Software Systems for Heterogeneous Hardware


3-7 February 2020

Responsable de l'activité

Alberto LERNER


Dr. Alberto Lerner, UNIFR

Prof. Dr. Philippe Cudré-Mauroux, UNIFR

Prof. Dr. Pascal Felber, UNINE

  • Prof. Paolo Ienne (EPFL) – High-Level Synthesis
  • Prof. Onur Mutlu (ETH) – In-Memory Computing
  • Dr. Jian Ouyang (Chief Hardware Architect – Baidu, China) – ML Acceleration
  • Prof. Yong Ho Song (Hanyang University, South Korea and Samsumg) – Near-Data Processing

It used to be that any computation done within a data management system (or any system for that matter) was handled exclusively by a general-purpose CPU. With the advent of GPGPUs and tools such as CUDA or OpenCL, the GPUs became another source of compute power -- in many scenarios, much faster than a CPU. The list of specialized hardware and their programming abstractions has kept growing ever since: TPUs and Tensor Flow, programmable switches and P4, FPGA and VHDL, 'smart' SSDs and in-storage computations, just to name a few. These 'accelerators,' as these faster sources of specialized compute power are called, would have been useful but not too influential, if it weren't for another paradigm shift. CPUs are not getting faster as they used to be. People in the computer architecture field refer to the end of Moore's Law and Dennard's Scaling. Put it simply, performance improvements are not going to come from writing better software for increasingly parallel hardware, as we have done from the mid aughts. Performance will come from the tight collaboration between specialized hardware and the right abstractions/optimizations to unlock their power. That's why we've been seeing so many specific accelerators. In this gathering, we'll call up on the new hardware experts and ask them to guide system software students through the new potential areas of research. Our goal is to inform a new generation of students about the ongoing confluence of hardware and software as the next source for scalable systems.

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Deadline for registration 03.02.2020
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